It was found that the dielectric permittivity is almost constant

in the above frequency range, having approximately the same value as at lower learn more frequencies. The loss tangent is also almost constant with frequency. Finally, a comparison between the performance of CPW TLines on PSi, trap-rich HR Si, quartz, and standard low-resistivity CMOS Si was made in the above frequency range. An almost equal performance was obtained between the trap-rich HR Si, PSi, and quartz. At 210 GHz, porous Si showed an attenuation as low as 1 dB/mm and the quality factor was ~30. This performance is added to the other advantages of PSi compared to other Si-based substrates, e.g., its compatibility with the low-resistivity CMOS substrate (permitting co-integration of CMOS logic with RF and millimeter-wave devices on the same substrate) and its low achievable permittivity). All the above make PSi an excellent local substrate on the Si wafer for RF and millimeter-wave device integration on the Si chip, paving the way towards the digital/RF analog system-on-chip (SoC) of the future. Acknowledgements The trap-rich high-resistivity Si wafers were provided by UCL Belgium (Jean-Pierre Raskin), while measurements in the frequency range 140 to 210 GHz of the CPW TLines were conducted in the facilities of VTT, Helsinki, Finland (arranged by A. Markus) during a visit of

P. Sarafis to VTT. This work was supported by the Selleck NCT-501 EU Network of PD184352 (CI-1040) Excellence ‘Nanofunction’ through the EU 7th Framework Programme for Research under Contract

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